Seven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic

This paper attempts to come up with a proposed configuration of Multilevel inverters lesser number switches that are smaller in size, cost and higher efficiency. Designing an inverter topology proper control technique is the major challenge. cascaded H-Bridge (CHB) more popular among existing configurations multilevel (MLI). Even though it can produce levels, needs accommodate huge for levels. The focus this reduce components same voltage level H- Bridge configuration. In addition that, generating gating pulses difficult when there asymmetry switches. A new symmetrical series/parallel reduced switch count pulse width modulation (PWM) implemented digital logic generate required total harmonic distortion (THDI) output current PWM technique. simulation has been carried out MATLAB/Simulink software both R (resistive) R-L (resistive -inductive) loads.